1. Field of the Invention
This invention relates to a system for controlling access to a common bus by a plurality of data handling devices in a computer system, and more particularly to a system that establishes priority of bus access among the various devices.
2. Description of the Prior Art
A typical data processor includes a central processing unit (CPU) in which arithmetic operations are performed, a memory controller unit (MCU) for controlling data to and from data storage equipment, a peripheral processing unit (PPU) for processing data to and from input/output equipment and other peripherals, and a system service unit (SSU) for monitoring power, supplying clock signals and the like to other units. The relative size and capacity of the different units vary as a function of the particular data processing operation of interest. In special purpose data processors, i.e., data processors designed to perform a limited number of specific operations, the capacity and number of the different units can be established to conform with the user's needs. In a general purpose multiprocessor, however, it is sometimes the practice to provide a common bus and to connect to the bus individual units in relative numbers dictated by the user's needs. In such system, known as a multiprocessor, improved efficiency can be realized by establishing a priority system so that a given data handling unit can obtain access to the bus before some other given data unit. A versatile priority system can permit flexible use of system resources to accommodate a variety of users' needs.